MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 778

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
35.4 Functional Description
35.4.1 PDB Pre-trigger and Trigger Outputs
The PDB contains a counter whose output is compared against several different digital
values. If the PDB is enabled, a trigger input event will reset the counter and make it start
to count. A trigger input event is defined as a rising edge being detected on selected
trigger input source or software trigger being selected and SC[SWTRIG] is written with
1. For each channel, delay m determines the time between assertion of the trigger input
event to the point at which changes in the pre-trigger m output signal is initiated. The
time is defined as:
Each channel is associated with one ADC block. PDB channel n pre-trigger outputs 0 to
M and trigger output is connected to ADC hardware trigger select and hardware trigger
inputs. The pre-triggers are used to precondition the ADC block prior to the actual
trigger. The ADC contains M sets of configuration and result registers, allowing it to
operate in a ping-pong fashion, alternating conversions between M different analog
sources. The pre-trigger outputs are used to specify which signal will be sampled next.
When pre-trigger m is asserted, the ADC conversion is triggered with set m of the
configuration and result registers.
The waveforms shown in the following diagram illuminate the pre-trigger and trigger
outputs of PDB channel n. The delays can be independently set via the CHnDLYm
registers. And the pre-triggers can be enabled or disabled in CHnC1[EN[m]].
778
• Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) +
• Add one additional peripheral clock cycle to determine the time at which the channel
2 peripheral clock cycles
trigger output change.
DLY2
15–0
Field
These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter
is equal to the DLY1. Reading these bits returns the value of internal register that is effective for the
current PDB cycle.
PDB Pulse-Out Delay 2
These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is
equal to the DLY2. Reading these bits returns the value of internal register that is effective for the current
PDB cycle.
PDBx_POnDLY field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Description
Freescale Semiconductor, Inc.