MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 446

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Reset
Memory map/register definition
21.3.23 TCD Last Source Address Adjustment (DMA_TCD_SLAST)
Addresses: 4000_8000h base + 100Ch offset + (32d × n), where n = 0d to 15d
* Notes:
•
21.3.24 TCD Destination Address (DMA_TCD_DADDR)
Addresses: 4000_8000h base + 1010h offset + (32d × n), where n = 0d to 15d
* Notes:
•
446
Bit
Bit
W
W
R
R
x = Undefined at reset.
x = Undefined at reset.
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
31
31
NBYTES
SLAST
31–0
Field
Field
9–0
30
30
29
29
28
28
DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued)
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via
preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
Last source Address Adjustment
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
27
27
26
26
25
25
24
24
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
23
DMA_TCDn_SLAST field descriptions
22
22
21
21
20
20
19
19
18
18
17
17
DADDR
SLAST
16
16
15
15
Description
Description
14
14
13
13
12
12
11
11
10
10
9
9
8
8
Freescale Semiconductor, Inc.
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0