MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1407

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

While using AC97 in two-channel mode (CR[TCHEN] = 1), it is recommended that the
received tag is not stored in the Rx FIFO (ACNT[TIF] = 0). If you need to update the
ATAG register and also issue a RD/WR command (in a single frame), it is recommended
that the ATAG register is updated prior to issuing a RD/WR command.
46.4.1.5.1 AC97 fixed mode (ACNT[FV] = 0)
In fixed mode, I
(ACNT[FRDIV) that decide the number of frames for which the I
operating for one frame. The following shows the slot assignments in a valid transmit
frame:.
While receiving, bit 15 of the tag slot is checked to see if the codec is ready. If this bit is
set, the frame is received. The received tag provides the information about slots
containing valid data. If the corresponding tag bit is valid, the command address (slot #1)
and command data (slot #2) values are stored in the corresponding registers. The received
data (slot #3–12) is then stored in the receive FIFO (for valid slots).
46.4.1.5.2 AC97 variable mode (ACNT[FV] = 1)
In variable mode, the transmit slots that should contain data in the current frame are
determined by the SLOTREQ bits received in the previous frame. While receiving, if the
codec is ready, the frame is received and the SLOTREQ bits are stored for scheduling
transmission in the next frame.
The ACCST, ACCEN and ACCDIS registers helps determine which transmit slots are
active. This information is used to ensure that I
down/inactive channels.
46.4.2 I
The I
Freescale Semiconductor, Inc.
• Slot 0: The tag value (written by the user program)
• Slot 1: If RD/WR command, command address
• Slot 2: If WR command, command data
• Slot 3–12: Transmit FIFO data, depending on the valid slots indicated by the TAG
value
2
S uses the following clocks:
2
S clocking
2
S transmits in accordance with the AC97 frame rate divider bits
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
S does not transmit data for powered-
Chapter 46 Integrated interchip sound (I2S)
2
S should be idle, after
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