MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 649

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
30.2.1 CRC Data Register (CRC_CRC)
The CRC data register contains the value of the seed, data, and checksum. When the
CTRL[WAS] bit is set, any write to the data register is regarded as the seed value. When
the CTRL[WAS] bit is cleared, any write to the data register is regarded as data for
general CRC computation.
In 16-bit CRC mode, the HU and HL fields are not used for programming the seed value,
and reads of these fields return an indeterminate value. In 32-bit CRC mode, all fields are
used for programming the seed value.
When programming data values, the values can be written 8 bits, 16 bits, or 32 bits at a
time, provided all bytes are contiguous; with MSB of data value written first.
After all data values are written, the CRC result can be read from this data register. In 16-
bit CRC mode, the CRC result is available in the LU and LL fields. In 32-bit CRC mode,
all fields contain the result. Reads of this register at any time return the intermediate CRC
value, provided the CRC module is configured.
Address: CRC_CRC is 4003_2000h base + 0h offset = 4003_2000h
Freescale Semiconductor, Inc.
Bit
W
R
4003_2000
4003_2004
4003_2008
Absolute
address
(hex)
31
1
31–24
Field
HU
30
1
29
1
CRC Data Register (CRC_CRC)
CRC Polynomial Register (CRC_GPOLY)
CRC Control Register (CRC_CTRL)
28
1
HU
CRC High Upper Byte
In 16-bit CRC mode (the CTRL[TCRC] bit is 0), this field is not used for programming a seed value. In 32-
bit CRC mode (the CTRL[TCRC] bit is 1), values written to this field are part of the seed value when the
CTRL[WAS] bit is 1. When the CTRL[WAS] bit is 0, data written to this field is used for CRC checksum
generation in both 16-bit and 32-bit CRC modes.
27
1
26
1
25
1
24
1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
1
Register name
22
1
CRC_CRC field descriptions
21
1
Table continues on the next page...
20
1
HL
CRC memory map
19
1
18
1
17
1
16
1
15
1
Description
14
1
13
1
12
1
(in bits)
Width
LU
Chapter 30 Cyclic redundancy check (CRC)
32
32
32
11
1
10
1
Access
1
9
R/W
R/W
R/W
1
8
1
7
Reset value
0000_1021h
0000_0000h
1
6
FFFF_
FFFFh
1
5
4
1
LL
1
3
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30.2.1/
30.2.2/
30.2.3/
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