MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 119

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

3.8.2.2 External Clock Options
By default each FTM is clocked by the internal bus clock (the FTM refers to it as system
clock). Each module contains a register setting that allows the module to be clocked from
an external clock instead. There are two external FTM_CLKINx pins that can be selected
by any FTM module via the SOPT4 register in the SIM module.
3.8.2.3 Fixed frequency clock
The fixed frequency clock for each FTM is MCGFFCLK.
3.8.2.4 FTM Interrupts
The FlexTimer has multiple sources of interrupt. However, these sources are OR'd
together to generate a single interrupt request to the interrupt controller. When an FTM
interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the
exact interrupt source.
3.8.2.5 FTM Fault Detection Inputs
The following fault detection input options for the FTM modules are selected via the
SOPT4 register in the SIM module. The external pin option is selected by default.
3.8.2.6 FTM Hardware Triggers
The FTM synchronization hardware triggers are connected in the chip as follows:
Freescale Semiconductor, Inc.
• FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output
• FTM0 FAULT1 = FTM0_FLT1 pin or CMP1 output
• FTM0 FAULT2 = FTM0_FLT2 pin or CMP2 output
• FTM0 FAULT3 = FTM0_FLT3 pin
• FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output
• FTM1 FAULT1 = CMP1 output
• FTM1 FAULT2 = CMP2 output
• FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output
• FTM2 FAULT1 = CMP1 output
• FTM2 FAULT2 = CMP2 output
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 3 Chip Configuration
119