MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 66

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Core modules
66
0x0000_0054
0x0000_0058
0x0000_005C
0x0000_0060
0x0000_0064
0x0000_0068
0x0000_006C
0x0000_0070
0x0000_0074
0x0000_0078
0x0000_007C
0x0000_0080
0x0000_0084
0x0000_0088
0x0000_008C
0x0000_0090
0x0000_0094
0x0000_0098
0x0000_009C
0x0000_00A0
0x0000_00A4
0x0000_00A8
0x0000_00AC
0x0000_00B0
0x0000_00B4
0x0000_00B8
0x0000_00BC
0x0000_00C0
Address
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Vector
Table 3-4. Interrupt vector assignments (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IRQ
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
non-IPR
register
number
NVIC
Table continues on the next page...
2
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
register
number
NVIC
IPR
3
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
MCM
Flash memory
Flash memory
Mode Controller
LLWU
WDOG
—
I
I
SPI0
SPI1
—
CAN0
CAN0
CAN0
CAN0
2
2
C0
C1
Source module
DMA channel 5 transfer complete
DMA channel 6 transfer complete
DMA channel 7 transfer complete
DMA channel 8 transfer complete
DMA channel 9 transfer complete
.
DMA channel 10 transfer complete
DMA channel 11 transfer complete
DMA channel 12 transfer complete
DMA channel 13 transfer complete
DMA channel 14 transfer complete
DMA channel 15 transfer complete
DMA error interrupt channels 0-15
Normal interrupt
Command complete
Read collision
Low-voltage detect, low-voltage warning
Low Leakage Wakeup
NOTE: The LLWU interrupt must not
Watchdog interrupt
—
—
—
Single interrupt vector for all sources
Single interrupt vector for all sources
—
OR'ed Message buffer (0-15)
Bus Off
Error
Transmit Warning
be masked by the interrupt
controller to avoid a scenario
where the system does not fully
exit stop mode on an LLS
recovery.
Source description
Freescale Semiconductor, Inc.