MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 722

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definitions
32.7.4 CMP Status and Control Register (CMPx_SCR)
Addresses: CMP0_SCR is 4007_3000h base + 3h offset = 4007_3003h
722
FILT_PER
Reserved
DMAEN
SMELB
Field
Reset
Field
7–0
Read
IER
Write
7
6
5
4
Bit
CMP1_SCR is 4007_3008h base + 3h offset = 4007_300Bh
CMP2_SCR is 4007_3010h base + 3h offset = 4007_3013h
Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used
to determine the sampling period.
This read-only field is reserved and always has the value zero.
DMA Enable Control
The DMAEN bit enables the DMA transfer triggered from the CMP module. When this bit is set, a DMA
request is asserted when the CFR or CFF bit is set.
0
1
Stop Mode Edge/Level Interrupt Control
This bit controls whether the CFR and CFF bits are edge sensitive or level sensitive in Stop mode.
NOTE: This bit should always be programmed to 0 to keep the comparator working and to wake up the
0
1
Comparator Interrupt Enable Rising
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
7
0
0
DMA disabled.
DMA enabled.
CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be
asserted when COUT is low.
CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to
assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.
MCU.
DMAEN
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
CMPx_SCR field descriptions
CMPx_FPR field descriptions
SMELB
Table continues on the next page...
0
5
IER
0
4
Description
Description
IEF
0
3
CFR
w1c
0
2
Freescale Semiconductor, Inc.
CFF
w1c
0
1
COUT
0
0