MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 361

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

18.3.8 Region Descriptor Alternate Access Control n
Since software may adjust only the access controls within a region descriptor
(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-
bit entity is available. Writing to this register does not affect the descriptor’s valid bit.
Addresses: 4000_D000h base + 800h offset + (4d × n), where n = 0d to 11d
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
R
R
M7WE
M6WE
M5WE
M7RE
M6RE
M5RE
Field
31
30
29
28
27
26
M2SM
[bit 0]
31
15
0
0
(MPU_RGDAACn)
30
14
0
0
Bus master 7 read enable.
0
1
Bus master 7 write enable
0
1
Bus master 6 read enable.
0
1
Bus master 6 write enable
0
1
Bus master 5 read enable.
0
1
Bus master 5 write enable
M2UM
Bus master 7 reads terminate with an access error and the read is not performed
Bus master 7 reads allowed
Bus master 7 writes terminate with an access error and the write is not performed
Bus master 7 writes allowed
Bus master 6 reads terminate with an access error and the read is not performed
Bus master 6 reads allowed
Bus master 6 writes terminate with an access error and the write is not performed
Bus master 6 writes allowed
Bus master 5 reads terminate with an access error and the read is not performed
Bus master 5 reads allowed
29
13
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
MPU_RGDAACn field descriptions
27
11
0
0
Table continues on the next page...
26
10
0
0
M1SM
25
0
0
9
24
0
0
8
Description
M1UM
23
0
0
7
22
0
0
6
M3SM
Chapter 18 Memory Protection Unit (MPU)
21
0
0
5
20
0
0
4
M0SM
M3UM
19
0
0
3
18
0
0
2
M0UM
17
0
0
1
M2SM
[-14:1]
16
0
0
0
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