MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 344

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
When a master makes a request to a slave port, the slave port checks if the new
requesting master's priority level is higher than that of the master that currently has
control over the slave port, unless the slave port is in a parked state. The slave port
performs an arbitration check at every clock edge to ensure that the proper master, if any,
has control of the slave port.
The following table describes possible scenarios based on the requesting master port:
17.3.3.3 Round-robin priority operation
When operating in Round-Robin mode, each master is assigned a relative priority based
on the master port number. This relative priority is compared to the master port number
(ID) of the last master to perform a transfer on the slave bus. The highest priority
requesting master becomes owner of the slave bus at the next transfer boundary,
accounting for locked and fixed-length burst transfers. Priority is based on how far ahead
the ID of the requesting master is to the ID of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to
that port until another master makes a request to the same slave port. The next master in
line is granted access to the slave port at the next transfer boundary, or possibly on the
next clock cycle if the current master has no pending access request.
As an example of arbitration in Round-Robin mode, assume the crossbar is implemented
with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and
master 0, 4 and 5 make simultaneous requests, they are serviced in the order 4, 5, and
then 0.
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Both of the following are true:
Both of the following are true:
The master is running an undefined length burst transfer.
The requesting master's priority level is lower than the current
master.
• The current master is not running a transfer.
• The new requesting master's priority level is higher
• The current master is running a fixed length burst
• The requesting master's priority level is higher than that
than that of the current master.
transfer or a locked transfer.
of the current master.
Table 17-29. How AXBS grants control of a slave port to a master
When
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
At the next clock edge
At the end of the burst transfer or locked transfer
At the next arbitration point
NOTE: Arbitration points for an undefined length burst are
At the conclusion of one of the following cycles:
Then AXBS grants control to the requesting master
• An IDLE cycle
• A non-IDLE cycle to a location other than the current
slave port
defined in the MGPCR for each master.
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