MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 98

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memories and Memory Interfaces
3.5.3.5 SRAM arbitration and priority control
The MCM's SRAMAP register controls the arbitration and priority schemes for the two
SRAM arrays.
3.5.4 SRAM Controller Configuration
This section summarizes how the module has been configured in the chip.
98
System memory map
Power management
Power management
• Core code and non-core master
• Core system and non-core master
controller (PMC)
Topic
Cortex-M4
Two non-core masters cannot access SRAM simultaneously.
The required arbitration and serialization is provided by the
crossbar switch. The SRAM_{L,U} arbitration is controlled by
the SRAM controller based on the configuration bits in the
MCM module.
Burst-access cannot occur across the 0x2000_0000 boundary
that separates the two SRAM arrays. The two arrays should be
treated as separate memory ranges for burst accesses.
Crossbar
switch
core
Table 3-38. Reference links to related information
Related module
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 3-26. SRAM controller configuration
MPU
MPU
Table continues on the next page...
SRAM controller
NOTE
NOTE
System memory map
Power management
Reference
PMC
Transfers
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