MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 522

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
522
OSCINIT
IREFST
CLKST
PLLST
IRCST
Field
3–2
5
4
1
0
While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated
off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV [4:0] bits
in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay
cleared until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN =0 also
causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has
reacquired lock. Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated
off until the LOCK bit is asserted again.
0
1
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a
write to the PLLS bit due to internal synchronization between clock domains.
0
1
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0
1
Clock Mode Status
These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the
CLKS bits due to internal synchronization between clock domains.
00
01
10
11
OSC Initialization
This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have
completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. Refer to the OSC
module's detailed description for more information.
Internal Reference Clock Status
The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The
IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization
between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled,
either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit .
0
1
PLL is currently unlocked.
PLL is currently locked.
Source of PLLS clock is FLL clock.
Source of PLLS clock is PLL clock.
Source of FLL reference clock is the external reference clock.
Source of FLL reference clock is the internal reference clock.
Source of internal reference clock is the slow clock (32 kHz IRC).
Source of internal reference clock is the fast clock (2 MHz IRC).
Encoding 0 — Output of the FLL is selected (reset default).
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Encoding 3 — Output of the PLL is selected.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
MCG_S field descriptions (continued)
Description
Freescale Semiconductor, Inc.