MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1248

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
45.4.2 Block Attributes Register (SDHC_BLKATTR)
This register is used to configure the number of data blocks and the number of bytes in
each block.
Address: SDHC_BLKATTR is 400B_1000h base + 4h offset = 400B_1004h
1248
Bit
W
R
Reserved
31
BLKCNT
0
31–16
Field
Field
1–0
30
0
29
0
28
0
This register contains the 32-bit system memory address for a DMA transfer. Since the address must be
word (4 bytes) align, the least 2 bits are reserved, always 0. When the SDHC stops a DMA transfer, this
register points to the system address of the next contiguous data position. It can be accessed only when
no transaction is executing (i.e. after a transaction has stopped). Read operation during transfers may
return an invalid value. The host driver shall initialize this register before starting a DMA transaction. After
DMA has stopped, the system address of the next contiguous data position can be read from this register.
This register is protected during a data transfer. When data lines are active, write to this register is
ignored. The host driver shall wait, until the PRSSTAT[DLA] is cleared, before writing to this register.
The SDHC internal DMA does not support a virtual memory system. It only supports continuous physical
memory access. And due to AHB burst limitations, if the burst must cross the 1 KB boundary, SDHC will
automatically change SEQ burst type to NSEQ.
Since this register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it automatically
alters the value of internal address counter, so SW cannot change this register when IRQSTAT[TC] bit is
set.
This read-only field is reserved and always has the value zero.
Blocks Count For Current Transfer
This register is enabled when the XFERTYP[BCEN] is set to 1 and is valid only for multiple block
transfers. For single block transfer, this register will always read as 1. The host driver shall set this
register to a value between 1 and the maximum block count. The SDHC decrements the block count after
each block transfer and stops when the count reaches zero. Setting the block count to 0 results in no data
blocks being transferred.
This register should be accessed only when no transaction is executing (that is after transactions are
stopped). During data transfer, read operations on this register may return an invalid value and write
operations are ignored.
When saving transfer content as a result of a suspend command, the number of blocks yet to be
transferred can be determined by reading this register. The reading of this register should be applied after
transfer is paused by stop at block gap operation and before sending the command marked as suspend.
This is because when suspend command is sent out, SDHC will regard the current transfer is aborted and
change BLKCNT back to its original value instead of keeping the dynamical indicator of remained block
count.
27
0
26
0
25
0
BLKCNT
SDHC_DSADDR field descriptions (continued)
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
SDHC_BLKATTR field descriptions
22
0
21
0
Table continues on the next page...
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
BLKSIZE
0
7
0
6
0
5
4
0
0
3
0
2
0
1
0
0