MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1098

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
42.4.2.4 Transmit First In First Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The
TX FIFO holds 4 words, each consisting of a command field and a data field. The
number of entries in the TX FIFO is device-specific. SPI commands and data are added
to the TX FIFO by writing to the DSPI PUSH TX FIFO Register (PUSHR). TX FIFO
entries can only be removed from the TX FIFO by being shifted out or by flushing the
TX FIFO.
The TX FIFO Counter field (TXCTR) in the DSPI Status Register (SR) indicates the
number of valid entries in the TX FIFO. The TXCTR is updated every time the DSPI
_PUSHR is written or SPI data is transferred into the shift register from the TX FIFO.
The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the
next transfer. The TXNXTPTR contains the positive offset from TXFR0 in number of
32-bit registers. For example, TXNXTPTR equal to two means that the TXFR2 contains
the SPI data and command for the next transfer. The TXNXTPTR field is incremented
every time SPI data is transferred from the TX FIFO to the shift register. The maximum
value of the field is equal to the maximum implemented TXFR register number and it
rolls over after reaching the maximum.
42.4.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by
writing to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in
the SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controller
indicates that a write to PUSHR is complete. Writing a '1' to the TFFF bit also clears it.
The TFFF can generate a DMA request or an interrupt request. See
Transmit FIFO Fill
Interrupt or DMA Request
for details.
The DSPI ignores attempts to push data to a full TX FIFO, the state of the TX FIFO does
not change and no error condition is indicated.
42.4.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift
register. Entries are transferred from the TX FIFO to the shift register and shifted out as
long as there are valid entries in the TX FIFO. Every time an entry is transferred from the
TX FIFO to the shift register, the TX FIFO Counter decrements by one. At the end of a
transfer, the TCF bit in the SR is set to indicate the completion of a transfer. The TX
FIFO is flushed by writing a '1' to the CLR_TXF bit in MCR.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
1098
Freescale Semiconductor, Inc.