MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 947

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

39.5 CMT External Signal Descriptions
This table shows the description of the external signal.
39.5.1 CMT_IRO — Infrared Output
This output signal is driven by the modulator output when MSC[MCGEN] is set and
OC[IROPEN] is set. The CMT_IRO signal starts a valid transmission with a delay, after
MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits.
The following table shows how to calculate this delay.
If MSC[MCGEN] bit is cleared and OC[IROPEN] bit is set, the signal is driven by
OC[IROL] bit. This enables user software to directly control the state of the CMT_IRO
signal by writing to OC[IROL] bit. If OC[IROPEN] bit is cleared, the signal is disabled
and is not driven by the CMT module. Therefore, CMT can be configured as a modulo
timer for generating periodic interrupts without causing signal activity.
39.6 Memory Map/Register Definition
The following registers control and monitor CMT operation.
The address of a register is the sum of a base address and an address offset. The base
address is defined at the chip level. The address offset is defined at the module level.
Freescale Semiconductor, Inc.
CMT_IRO
Signal
MSC[CMTDIV] = 0
MSC[CMTDIV] > 0
Infrared Output
Description
Condition
Table 39-3. CMT_IRO signal delay calculation
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 39-2. CMT Signal Descriptions
Chapter 39 Carrier Modulator Transmitter (CMT)
Delay (bus clock cycles)
(PPS{PPSDIV] × 2) + 3
PPS[PPSDIV] + 2
I/O
O
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