MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 709

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

There are some situations where external system activity causes radiated or conducted
noise emissions or excessive V
when the MCU cannot be placed in Wait or Normal Stop or I/O activity cannot be halted,
these recommended actions may reduce the effect of noise on the accuracy:
31.6.2.4 Code width and quantization error
The ADC quantizes the ideal straight-line transfer function into 65536 steps (in 16-bit
mode). Each step ideally has the same height (1 code) and width. The width is defined as
the delta between the transition points to one code and the next. The ideal code width for
an N bit converter (in this case N can be 16, 12, 10, or 8), defined as 1 LSB, is:
There is an inherent quantization error due to the digitization of the result. For 8-bit, 10-
bit, or 12-bit conversions, the code transitions when the voltage is at the midpoint
between the points where the straight line transfer function is exactly represented by the
actual transfer function. Therefore, the quantization error will be ± 1/2 LSB in 8-bit, 10-
bit, or 12-bit modes. As a consequence, however, the code width of the first (0x000)
conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB.
Freescale Semiconductor, Inc.
• There is no I/O switching, input or output, on the MCU during the conversion.
• Place a 0.01 μF capacitor (C
• Average the result by converting the analog input many times in succession and
• Reduce the effect of synchronous noise by operating off the asynchronous clock
improves noise issues, but affects the sample rate based on the external analog source
resistance).
dividing the sum of the results. Four samples are required to eliminate the effect of a
1 LSB, one-time error.
(ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged
out.
• For software triggered conversions, immediately follow the write to the SC1
• For Normal Stop mode operation, select ADACK as the clock source. Operation
register with a wait instruction or stop instruction.
in Normal Stop reduces V
stop recovery.
Figure 31-99. Ideal code width for an N bit converter
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
DD
AS
LSB
noise is coupled into the ADC. In these situations, or
DD
) on the selected input channel to V
noise but increases effective conversion time due to
Chapter 31 Analog-to-Digital Converter (ADC)
REFL
or V
SSA
(this
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