MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 950

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Memory Map/Register Definition
39.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)
This data register contain the secondary high value for generating the carrier output.
Address: CMT_CGH2 is 4006_2000h base + 2h offset = 4006_2002h
* Notes:
39.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2)
This data register contain the secondary low value for generating the carrier output.
Address: CMT_CGL2 is 4006_2000h base + 3h offset = 4006_2003h
* Notes:
950
x = Undefined at reset.
x = Undefined at reset.
Reset
Field
Reset
Field
Read
7–0
Read
7–0
Write
Write
SH
SL
Bit
Bit
Secondary Carrier High Time Data Value
When selected, these bits contain the number of input clocks required to generate the carrier high time
period. When operating in Time mode, this register is never selected. When operating in FSK mode, this
register and the primary register pair are alternately selected under control of the modulator. The
secondary carrier high time value is undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
Secondary Carrier Low Time Data Value
When selected, these bits contain the number of input clocks required to generate the carrier low time
period. When operating in Time mode, this register is never selected. When operating in FSK mode, this
register and the primary register pair are alternately selected under control of the modulator. The
secondary carrier low time value is undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
x*
x*
7
7
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
x*
x*
6
6
CMT_CGH2 field descriptions
CMT_CGL2 field descriptions
x*
x*
5
5
x*
x*
4
4
Description
Description
SH
SL
x*
x*
3
3
x*
x*
2
2
Freescale Semiconductor, Inc.
x*
x*
1
1
x*
x*
0
0

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