MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1417

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The following figure is illustrates a transmission case where:
46.4.7 Reset
The I
46.5 Initialization/application information
The correct sequence to initialize the I
Freescale Semiconductor, Inc.
1. Issue a power-on or I
• TCR[TXDIR] and TCR[TFDIR] are set
• CR[TFRCLKDIS] is set a few frames after clearing CR[TE]
• ISR[TRFC] is set at the frame boundary after CR[TE] is cleared. Once software
Figure 46-60. CR[TFRCLKDIS] assertion in subsequent frame after disabling CR[TE]
• Power-on reset—This reset clears the CR[I2SEN] bit, which disables the I
• I
services this interrupt and later sets CR[TFRCLKDIS] bit, the ISR[TRFC] bit is set
again at next frame boundary.
other status and control bits in the I
register
status bits are reset to the same state produced by the power-on reset. The I
bits, including those in CR register, are unaffected. The I
selective reset of the I
affecting other peripherals.
2
2
S reset—The I
S is affected by the following types of reset:
definition.
CR[TFCLDIS]
ISR[TFRC]
Tx Data
CR[TE]
2
S reset is generated when the CR[I2SEN] bit is cleared. The I
CLK
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
FS
2
2
S reset (CR[I2SEN] = 0).
S, without changing the present I
2
S is as follows:
2
S are affected as described in
w1c
Chapter 46 Integrated interchip sound (I2S)
2
2
S control bits and without
S reset is useful for
Memory map/
2
2
S. All
S control
2
S
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