MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1535

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

50.4.3.2 Selecting an IEEE 1149.1-2001 register
Access to the JTAGC data registers is achieved by loading the instruction register with
any of the JTAGC block instructions while the JTAGC is enabled. Instructions are shifted
in via the Select-IR-Scan path and loaded in the Update-IR state. At this point, all data
register access is performed via the Select-DR-Scan path.
The Select-DR-Scan path is used to read or write the register data by shifting in the data
(LSB first) during the Shift-DR state. When reading a register, the register value is loaded
into the IEEE 1149.1-2001 shifter during the Capture-DR state. When writing a register,
the value is loaded from the IEEE 1149.1-2001 shifter to the register during the Update-
DR state. When reading a register, there is no requirement to shift out the entire register
contents. Shifting may be terminated once the required number of bits have been
acquired.
50.4.4 JTAGC block instructions
The JTAGC block implements the IEEE 1149.1-2001 defined instructions listed in the
following table. This section gives an overview of each instruction; refer to the IEEE
1149.1-2001 standard for more details. All undefined opcodes are reserved.
Freescale Semiconductor, Inc.
IDCODE
EZPORT
SAMPLE/PRELOAD
SAMPLE
EXTEST
Factory debug reserved
Factory debug reserved
Factory debug reserved
ARM JTAG-DP Reserved
HIGHZ
ARM JTAG-DP Reserved
Instruction
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 50-3. 4-bit JTAG instructions
Table continues on the next page...
Code[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Selects device identification register for shift
Enables the EZPORT function for the SoC
Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
Selects boundary scan register for shifting and sampling
without disturbing functional operation
Selects boundary scan register while applying preloaded
values to output pins and asserting functional reset
Intended for factory debug only
Intended for factory debug only
Intended for factory debug only
This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
Selects bypass register while three-stating all output pins and
asserting functional reset
This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
Instruction Summary
Chapter 50 JTAG Controller (JTAGC)
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