MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 17

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Section Number
Freescale Semiconductor, Inc.
21.3.6
21.3.7
21.3.8
21.3.9
21.3.10
21.3.11
21.3.12
21.3.13
21.3.14
21.3.15
21.3.16
21.3.17
21.3.18
21.3.19
21.3.20
21.3.21
21.3.22
21.3.23
21.3.24
21.3.25
21.3.26
21.3.27
21.3.28
21.3.29
21.3.30
Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................427
Clear Enable Request Register (DMA_CERQ)...........................................................................................428
Set Enable Request Register (DMA_SERQ)...............................................................................................429
Clear DONE Status Bit Register (DMA_CDNE)........................................................................................430
Set START Bit Register (DMA_SSRT)......................................................................................................431
Clear Error Register (DMA_CERR)............................................................................................................432
Clear Interrupt Request Register (DMA_CINT).........................................................................................433
Interrupt Request Register (DMA_INT)......................................................................................................433
Error Register (DMA_ERR)........................................................................................................................436
Hardware Request Status Register (DMA_HRS)........................................................................................438
Channel n Priority Register (DMA_DCHPRIn)..........................................................................................440
TCD Source Address (DMA_TCDn_SADDR)...........................................................................................441
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................442
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................442
TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................443
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................444
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................445
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................446
TCD Destination Address (DMA_TCDn_DADDR)...................................................................................446
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................447
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................447
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................448
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........449
TCD Control and Status (DMA_TCDn_CSR)............................................................................................450
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................452
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
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