MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1259

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
Reserved
BWEN
15–12
BREN
WTA
Field
RTA
11
10
9
8
The SYSCTL[RSTA] does not effect this bit.A software reset does not effect this bit.
0b
1b
This read-only field is reserved and always has the value zero.
Buffer Read Enable
This status bit is used for non-DMA read transfers. The SDHC may implement multiple buffers to transfer
data efficiently. This read only flag indicates that valid data exists in the host side buffer. If this bit is high,
valid data greater than the watermark level exist in the buffer. This read only flag indicates that valid data
exists in the host side buffer.
0b
1b
Buffer Write Enable
This status bit is used for non-DMA write transfers. The SDHC can implement multiple buffers to transfer
data efficiently. This read only flag indicates if space is available for write data. If this bit is 1, valid data
greater than the watermark level can be written to the buffer.This read only flag indicates if space is
available for write data.
0b
1b
Read Transfer Active
This status bit is used for detecting completion of a read transfer.
This bit is set for either of the following conditions:
A transfer complete interrupt is generated when this bit changes to 0. This bit is cleared for either of the
following conditions:
0b
1b
Write Transfer Active
This status bit indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the
SDHC.
This bit is set in either of the following cases:
This bit is cleared in either of the following cases:
• After the end bit of the read command.
• When writing a 1 to the PROCTL[CREQ] to restart a read transfer.
• When the last data block as specified by block length is transferred to the system, that is all data
• When all valid data blocks have been transferred from SDHC internal buffer to the system and no
• After the end bit of the write command.
• When writing 1 to the PROCTL[CREQ] to restart a write transfer.
• After getting the CRC status of the last data block as specified by the transfer count (single and
• After getting the CRC status of any block where data transmission is about to be stopped by a stop
Power on reset or no card
Card inserted
Read disable, valid data less than the watermark level exist in the buffer.
Read enable, valid data greater than the watermark level exist in the buffer.
Write disable, the buffer can hold valid data less than the write watermark level.
Write enable, the buffer can hold valid data greater than the write watermark level.
No valid data
Transferring data
are read away from SDHC internal buffer.
current block transfers are being sent as a result of the stop at block gap request being set to 1.
multiple).
at block gap request.
SDHC_PRSSTAT field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 45 Secured digital host controller (SDHC)
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