MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 402

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Introduction
21.1.3 Features
The eDMA is a highly-programmable data-transfer engine optimized to minimize the
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the data packet
itself. The eDMA module features:
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Memory controller
Memory array
• All data movement via dual-address transfers: read from source, write to destination
• 16-channel implementation that performs complex data transfers with minimal
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
• Channel activation via one of three methods:
• Fixed-priority and round-robin channel arbitration
intervention from a host processor
operations
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• Internal data buffer, used as temporary storage to support 16-byte burst transfers
• Connections to the crossbar switch for bus mastering the data movement
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
Submodule
Table 21-2. Transfer control descriptor memory
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
This logic implements the required dual-ported controller,
managing accesses from the eDMA engine as well as
references from the internal peripheral bus. As noted earlier,
in the event of simultaneous accesses, the eDMA engine is
given priority and the peripheral transaction is stalled.
TCD storage is implemented using a single-port,
synchronous RAM array.
Description
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