MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 287

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

13.1.2.4.4 Very Low-Leakage Stop (VLLS3,2,1) Modes
This device contains three very low leakage modes: VLLS3, VLLS2, and VLLS1. When
a reference applies to all three low leakage modes, VLLS is used.
All three of the VLLS modes can be entered from normal run or VLPR.
The MCU enters the configured VLLS mode if:
In VLLS, the on-chip voltage regulator is in its stop-regulation state.
In VLLS, configure the LLWU module to enable the desired wakeup sources. The
available wakeup sources in VLLS are detailed LLWU's Chip Configuration details for
this device.
When entering VLLS, each I/O pin is latched as configured before executing VLLS.
Since all digital logic in the MCU is powered off, all port and peripheral data is lost
during VLLS. This information must be restored before ACKISO in the LLWU is set.
An asserted RESET pin exits any VLLS mode. This returns the device to normal run
mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits are set in the
SRSL register.
13.1.2.5 ARM Debug in Low Power Modes
When the MCU is secure the device disables/limits debugger operation. When the MCU
is unsecure, the ARM debugger can assert two power-up request signals:
When asserted while in run, wait, VLPR, or VLPW, the Mode Controller drives a
corresponding acknowledge for each signal (CDBGPWRUPACK, CSYSPWRUPACK).
When both requests are asserted, the Mode Controller handles attempts to enter stop and
VLPS by entering an emulated stop state. In this emulated stop state:
Freescale Semiconductor, Inc.
• In sleep-now or sleep-on-exit mode, the SLEEPDEEP bit is set in the System Control
• The device is configured as per
• System power up (SYSPWR bit in the Debug Port Control/Stat register)
• Debug power up (CDBGPWRUPREQ bit in the Debug Port Control/Stat register)
• The regulator is in stop regulation,
• The MCG-generated clock source is enabled,
• All system clocks, except core clock, are disabled,
• The debug module has access to core registers, and
• Access to the on-chip peripherals is blocked.
Register in the ARM core, and
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table
13-2.
Chapter 13 Mode Controller
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