MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 935

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
38.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)
Addresses: LPTMR0_PSR is 4004_0000h base + 4h offset = 4004_0004h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
31–7
Field
TMS
TEN
Field
TFC
30
2
1
0
0
29
0
28
0
The Timer Pin Polarity configures the polarity of the input source in Pulse Counter mode. The Timer Pin
Polarity should only be changed when the LPTMR is disabled.
0
1
Timer Free Running Counter
When clear the Timer Free Running Counter configures the LPTMR Counter Register to reset whenever
the Timer Compare Flag is set. When set, the Timer Free Running Counter configures the LPTMR
Counter Register to reset on overflow. The Timer Free Running Counter should only be altered when the
LPTMR is disabled.
0
1
Timer Mode Select
The Timer Mode Select configures the mode of the LPTMR. The Timer Mode Select should only be
altered when the LPTMR is disabled.
0
1
Timer Enable
When the Timer Enable bit is clear, it resets the LPTMR internal logic (including the LPTMR Counter
Register and Timer Compare Flag). When the Timer Enable bit is set, the LPTMR is enabled. When
writing 1 to this bit, bits LPTMR_CSR[5:1] should not be altered.
0
1
This read-only field is reserved and always has the value zero.
27
0
Pulse Counter input source is active high, and LPTMR Counter Register will increment on the rising
edge.
Pulse Counter input source is active low, and LPTMR Counter Register will increment on the falling
edge.
LPTMR Counter Register is reset whenever the Timer Compare Flag is set.
LPTMR Counter Register is reset on overflow.
Time Counter mode.
Pulse Counter mode.
LPTMR is disabled and internal logic is reset.
LPTMR is enabled.
26
0
25
0
24
LPTMRx_CSR field descriptions (continued)
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
LPTMRx_PSR field descriptions
21
0
Table continues on the next page...
20
0
19
0
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
Chapter 38 Low power timer (LPTMR)
0
9
0
8
0
7
0
6
PRESCALE
0
5
4
0
0
3
0
2
0
1
PCS
935
0
0