MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1516

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Initialization section
1516
BPEN[3:0]
PEN[3:0]
Register
GCR
AR
VSUPPLY[1:0]
RVTRIM[3:0]
BRATE[2:0]
DUTY[2:0]
LCDWAIT
LADJ[1:0]
LCLK[2:0]
Table 49-43. Initialization register values for example 1
SOURCE
LCDSTP
LCDIEN
BMODE
bit field
CPSEL
LCDEN
BLANK
BPEN0
BPEN1
BPEN2
BPEN3
BLINK
RVEN
PEN0
PEN1
PEN2
PEN3
Bit or
ALT
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
11111111
11111111
11111111
00000000
11111111
00000000
00000000
00000000
Binary
XXXX
value
XXX
101
111
XX
11
X
X
X
0
0
1
1
0
0
0
0
Table continues on the next page...
Disable charge pump.
Adjust the resistor bias network for different LCD glass capacitance.
or
Configure LCD charge pump clock source.
When VSUPPLY[1:0] = 11 and CPSEL = 0, the LCD must be externally
powered via V
LCD frame interrupts disabled.
LCD is "on" in Wait mode.
LCD is "on" in Stop mode.
Initialization is done before initializing the LCD controller,
Selects the external clock reference as the LCD clock input,
For 1/8 duty cycle, select closest value to the desired 30 Hz LCD frame
frequency (see
For 128 segments (8x16), select 1/8 duty cycle.
V
Trim value is determined by characterization.
No blinking.
Alternate bit is configured during LCD operation.
Blank bit is configured during LCD operation.
N/A; Blink Blank = 0; Blink Alternate = 1
N/A
Only 29 LCD pins need to be enabled.
Note: Any of the 63 LCD pins can be used, this allows flexibility in the
Eight backplane pins needed.
Note: Any LCD pin can be enabled to operate as a backplane.
Comment
IREG
is not used for this configuration.
hardware design.
LL3
Table
(see
49-31),
Table
49-38).
Freescale Semiconductor, Inc.