MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 80

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

System modules
3.3.7.2 MPU Logical Bus Master Assignments
The logical bus master assignments for the MPU are:
3.3.7.3 MPU Access Violation Indications
Access violations detected by the MPU are signaled to the appropriate bus master as
shown below:
3.3.7.4 Reset Values for RGD0 Registers
At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire
4 GB address space with read, write and execute permissions given to the core, debugger
and the DMA bus masters.
The following table shows the chip-specific reset values for RGD0 and RGDAAC0.
80
0
1
2
3
4
5
6
7
Core
Debugger
DMA
SDHC
MPU Logical Bus Master Number
Bus Master
Table 3-18. MPU Logical Bus Master Assignments
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 3-19. Access Violation Indications
Bus fault (interrupt vector #5) Note: To enable bus faults set the core's System
Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU
violations result in a hard fault (interrupt vector #3).
The STICKYERROR flag is set in the Debug Port Control/Status Register.
Interrupt vector #32
Interrupt vector #96
Core
Debugger
DMA
none
none
SDHC
none
none
Core Indication
Bus Master
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