MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 875

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In the case of legacy PWM synchronization, the OUTMASK register synchronization
depends on PWMSYNC bit according to the following description.
Freescale Semiconductor, Inc.
each rising edge of system clock
update OUTMASK register at
no =
with its buffer value
update OUTMASK
rising edge
of system
Figure 36-214. OUTMASK Register Synchronization Flowchart
clock ?
end
= yes
0 =
with its buffer value
update OUTMASK
OUTMASK is updated
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
by software trigger
SWSYNC
bit ?
end
= 1
1 =
software
trigger
SWOM
bit ?
0 =
SYNCHOM
begin
bit ?
= 0
end
= 1
end
0 =
enhanced PWM synchronization
update OUTMASK register by
1 =
HWOM
PWM synchronization
bit ?
SYNCMODE
hardware
wait hardware trigger n
trigger
with its buffer value
OUTMASK is updated
update OUTMASK
bit ?
by hardware trigger
clear TRIGn bit
HWTRIGMODE
= 1
Chapter 36 FlexTimer (FTM)
TRIGn
bit ?
bit ?
end
= 1
= 0
= 0
PWM synchronization
= 0
legacy
= 1
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