MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 495

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

23.4.2 Byte Test
The byte test implements more thorough a test of the watchdog timer. In this test, the
timer is split up into its constituent byte-wide stages that are run independently and tested
for time-out against the corresponding byte of the time-out value register. The following
figure explains the splitting concept:
Each stage is an 8-bit synchronous counter followed by combinational logic that
generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage.
In the test mode, when an individual byte, N, is tested, byte N – 1 is loaded forcefully
with 0xFF, and both these bytes are allowed to run off the clock source. By doing so the
overflow signal from stage N – 1 is generated immediately, enabling counter stage N.
The Nth stage runs and compares with the Nth byte of the time-out value register. In this
way, the byte N is also tested along with the link between it and the preceding stage. No
other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These
disabled stages (except the most significant stage of the counter) are loaded with a value
of 0xFF.
These two testing schemes achieve the overall aim of testing the counter functioning and
the compare and reset logic.
Freescale Semiconductor, Inc.
WDOG
Modulus Register
(Time-out Value)
Test
CLK
32-bit Timer
Byte 1
Stage 1
Byte
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 23-2. Watchdog Timer Byte Splitting
Nth Stage Overflow Enables N + 1th Stage
en
Stage 2
Byte 2
Reset Value (Hardwired)
Equality Comparison
Byte
en
Stage 3
Byte 3
Byte
en
Byte 4
Stage 4
Byte
Chapter 23 Watchdog Timer (WDOG)
Mod = = Timer?
WDOG
Reset
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