MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 588

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
Though the default configuration provides a high degree of flash acceleration, advanced
users may desire to customize the FMC buffer configurations to maximize throughput for
their use cases. When reconfiguring the FMC for custom use cases, do not program the
FMC's control registers while the flash memory is being accessed. Instead, change the
control registers with a routine executing from RAM in supervisor mode.
The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuning
of resources to suit particular applications' needs. The cache and two buffers are each
controlled individually. The register controls enable buffering and prefetching per
memory bank and access type (instruction fetch or data reference). The cache also
supports three types of LRU replacement algorithms:
As an application example: if both instruction fetches and data references are accessing
bank 0, control is available to send instruction fetches, data references, or both to the
cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for
either type of access. If both instruction fetches and data references are cached, the
cache's way resources may be divided in several ways between the instruction fetches and
data references.
In another application example, the cache can be configured for replacement from bank
0, while the single-entry buffer can be enabled for bank 1 only. This configuration is
ideal for applications that use bank 0 for program space and bank 1 for data space.
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• LRU per set across all four ways,
• LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and
• LRU with ways [0-2] for instruction fetches and way [3] for data fetches.
• The cache is configured for least recently used (LRU) replacement for all four
• The cache is configured for data or instruction replacement.
• The single-entry buffer is enabled.
ways.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.