MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1106

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
The master initiates the transfer by asserting the PCS signal to the slave. After the t
delay has elapsed, the master generates the first SCK edge and at the same time places
valid data on the master SOUT pin . The slave responds to the first SCK edge by placing
its first data bit on its slave SOUT pin.
At the second edge of the SCK the master and slave sample their SIN pins. For the rest of
the frame the master and the slave change the data on their SOUT pins on the odd-
numbered clock edges and sample their SIN pins on the even-numbered clock edges.
After the last clock edge occurs a delay of t
PCS signal. A delay of t
master.
42.4.4.3 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must
remain selected between several sequential serial transfers. The Continuous Selection
Format provides the flexibility to handle the following case. The Continuous Selection
Format is enabled for the SPI Configuration by setting the CONT bit in the SPI
command. The behavior of the PCS signals in the configurations is identical so only SPI
Configuration will be described.
1106
SCK (CPOL = 1)
SCK (CPOL = 0)
Master and Slave
t
t
MSB first (LSBFE = 0): MSB
CSC
ASC
LSB first (LSBFE = 1): LSB
t
Master SOUT/
DT =
Figure 42-73. DSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8)
Slave SIN
Master SIN/
Slave SOUT
Sample
=
= A fter SCK delay
PCSx/SS
P CS to SCK delay
Delay after Transfer (minimum CS negation time)
t
CSC
1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
DT
2
is inserted before a new frame transfer can be initiated by the
3
Bit 6
Bit 1
4
5
Bit 5
Bit 2
6
7
ASC
Bit 4
Bit 3
8
is inserted before the master negates the
9 10 11 12 13 14 15 16
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
Freescale Semiconductor, Inc.
MSB
LSB
t ASC
t
DT
CSC