MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 957

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

39.7 Functional Description
The CMT module consists primarily of clock divider, carrier generator and modulator.
39.7.1 Clock Divider
The CMT was originally designed to be based on 8 MHz bus clock that could be divided
by 1, 2, 4 or 8 times accordingly with the specification. To be compatible with higher bus
frequency, the Primary Prescaler (PPS) was developed to receive a higher frequency and
generate a clock enable signal called Intermediate Frequency (IF). This IF should be
approximately equal to 8 MHz and will work as a clock enable to the Secondary
Prescaler. The following figure shows the clock divider block diagram.
For compatibility with previous versions of CMT, when bus clock = 8 MHz, the PPS
should be configured to zero. The PPS counter is selected according to the bus clock to
generate an intermediate frequency approximately equal to 8 MHz.
39.7.2 Carrier Generator
The carrier generator resolution is 125 ns when operating with an 8 MHz intermediate
frequency signal and the Secondary Prescaler is set to divide by 1 (MSC[CMTDIV] =
00). The carrier generator can generate signals with periods between 250 ns (4 MHz) and
127.5 μs (7.84 kHz) in steps of 125 ns. The following table shows the relationship
between the clock divide bits and the carrier generator resolution, minimum carrier
generator period, and minimum modulator period.
Freescale Semiconductor, Inc.
Field
Bus clock
0
1
DMA transfer request and done are disabled
DMA transfer request and done are enabled
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 39-14. Clock Divider Block Diagram
CMT_DMA field descriptions (continued)
Primary
Prescaler
if_clk_enable
Description
Chapter 39 Carrier Modulator Transmitter (CMT)
Secondary
Prescaler
divider_enable
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