MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 573

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
B0MW[1:0]
Reserved
Reserved
S_B_INV
CRC[2:0]
B0DCE
B0ICE
18–17
15–8
Field
7–5
19
16
4
3
Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System
software is required to maintain memory coherency when any segment of the flash memory is
programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event
is completed and before the new memory image is accessed.
The bit setting definitions are for each bit in the field.
0
1
Invalidate Prefetch Speculation Buffer
This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be
invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are
immediately cleared. This bit always reads as zero.
0
1
Bank 0 Memory Width
This read-only field defines the width of the bank 0 memory.
00
01
1x
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Cache Replacement Control
This 3-bit field defines the replacement algorithm for accesses that are cached.
000
001
010
011
1xx
Bank 0 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0
1
Bank 0 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0
1
No cache way invalidation for the corresponding cache
Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
Speculation buffer and single entry buffer are not affected.
Invalidate (clear) speculation buffer and single entry buffer.
Do not cache data references.
Cache data references.
Do not cache instruction fetches.
Cache instruction fetches.
32 bits
64 bits
Reserved
LRU replacement algorithm per set across all four ways
Reserved
Independent LRU with ways [0-1] for ifetches, [2-3] for data
Independent LRU with ways [0-2] for ifetches, [3] for data
Reserved
FMC_PFB0CR field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 27 Flash Memory Controller (FMC)
573