MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 505

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

23.8.1 General Guideline
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is
to access both the bytes of a register, you must try to place the two 8-bit accesses one
after the other in your code.
23.8.2 Refresh and Unlock operations with 8-bit access
One exception condition that generates a reset to the system, is the write of any value
other than those required for a legal refresh/update sequence to the respective refresh and
unlock registers.
For an 8-bit access to these registers, writing a correct value requires at least two bus
clock cycles that means there is an invalid value in the registers for one cycle. Therefore,
the system is reset even if the intention is to write a correct value to the refresh/unlock
register. Keeping this in mind the exception condition for 8-bit accesses is slightly
modified. Whereas the match for a correct value for a refresh/unlock sequence is as per
the original definition, the match for an incorrect value is done byte-wise on the refresh/
unlock rather than for the whole 16-bit value. This means that if the high byte of the
refresh/unlock register contains any value other than high bytes of the two values making
up the sequence, it is treated as an exception condition, leading to a reset or interrupt-
then-reset. The same holds true for the lower byte of the refresh or unlock register. Let us
take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the
refresh register, as an example.
As shown in the preceding table, the refresh register holds its reset value initially.
Thereafter, two 8-bit accesses are performed on the register to write the first value of the
refresh sequence. No mismatch exception is registered on the intermediate write, Write1.
The sequence is completed by performing two more 8-bit accesses, writing in the second
value of the sequence for a successful refresh. It must be noted that the match of value2
Freescale Semiconductor, Inc.
Current Value
Write 1
Write 2
Write 3
Write 4
Write 5
WDOG_REFRESH[15:8]
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 23-14. Refresh for 8-bit Access
0xB4
0xB4
0xA6
0xB4
0xB4
0x02
WDOG_REFRESH[7:0]
0x80
0x02
0x02
0x02
0x80
0x80
Chapter 23 Watchdog Timer (WDOG)
Sequence value1 or
Sequence complete.
Value2 match.
value2 match
Value2 match
Value1 match
No match
No match
No match
Mismatch
exception
Yes
No
No
No
No
No
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