MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 739

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 32 Comparator (CMP)
Table 32-30. Comparator Sample/Filter Maximum Latencies (continued)
CR1[
CR1[
CR1[
CR0[FILTER
FPR[FILT_P
1
Mode #
Operation
Maximum Latency
EN]
WE]
SE]
_CNT]
ER]
7
1
1
0
> 0x01
0x01 - 0xFF
Windowed / Filtered mode
T
+ (CR0[FILTER_CNT] x
PD
FPR[FILT_PER] x T
) +
per
2T
per
1. T
represents the intrinsic delay of the analog component plus the polarity select logic. T
is the clock period of the
PD
SAMPLE
external sample clock. T
is the period of the bus clock.
per
32.9 CMP Interrupts
The CMP module is capable of generating an interrupt on either the rising or falling edge
of the comparator output (or both). The interrupt request is asserted when both SCR[IER]
bit and SCR[CFR] are set. It is also asserted when both SCR[IEF] bit and SCR[CFF] are
set. The interrupt is de-asserted by clearing either SCR[IER] or SCR[CFR] for a rising
edge interrupt, or SCR[IEF] and SCR[CFF] for a falling edge interrupt.
32.10 CMP DMA Support
Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When
DMA support (set SCR[DMAEN]) enables and the interrupt enables (set SCR[IER] or
SCR[IEF] or both), the corresponding change on COUT forces a DMA transfer request
rather than a CPU interrupt instead. When the DMA has completed the transfer, it sends a
dma_done signal that de-asserts the dma_request and clears the flag to allow a
subsequent change on comparator output to occur and force another DMA request.
32.11 Digital to Analog Converter Block Diagram
The following figure shows the block diagram of the DAC module. It contains a 64-tap
resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from
one of 64 distinct levels that outputs from DACO. It is controlled through DAC Control
register (DACCR). Its supply reference source can be selected from two sources V
and
in1
V
. The module can be powered down (disabled) when it is not used. When in disable
in2
mode, DACO is connected to the analog ground.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
739