MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 428

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
21.3.7 Clear Enable Request Register (DMA_CERQ)
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs. If NOP is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CERQ is 4000_8000h base + 1Ah offset = 4000_801Ah
428
Reserved
CERQ
CAER
NOP
Reset
Field
Read
5–4
3–0
Write
7
6
Bit
NOP
0
1
Clear All Enable Requests
0
1
This field is reserved.
Clear Enable Request
Clears the corresponding bit in ERQ
7
0
0
Normal operation
No operation, ignore the other bits in this register
Clear only the ERQ bit specified in the CERQ field
Clear all bits in ERQ
CAER
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
0
6
DMA_CERQ field descriptions
0
5
0
0
4
Description
0
3
0
2
CERQ
Freescale Semiconductor, Inc.
0
0
1
0
0