MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1256

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
This table shows that most responses with a length of 48 (R[47:0]) have 32-bit of the
response data (R[39:8]) stored in the CMDRSP0 register. Responses of type R1b (auto
CMD12 responses) have response data bits (R[39:8]) stored in the CMDRSP3 register.
Responses with length 136 (R[135:0]) have 120-bit of the response data (R[127:8]) stored
in the CMDRSP0, 1, 2, and 3 registers.
To be able to read the response status efficiently, the SDHC only stores part of the
response data in the command response registers. This enables the host driver to
efficiently read 32-bit of response data in one read cycle on a 32-bit bus system. Parts of
the response, the index field and the CRC, are checked by the SDHC (as specified by the
XFERTYP[CICEN] and the XFERTYP[CCCEN] bits) and generate an error interrupt if
any error is detected. The bit range for the CRC check depends on the response length. If
the response length is 48, the SDHC will check R[47:1], and if the response length is 136
the SDHC will check R[119:1].
Since the SDHC may have a multiple block data transfer executing concurrently with a
CMD_wo_DAT command, the SDHC stores the auto CMD12 response in the CMDRSP3
register. The CMD_wo_DAT response is stored in CMDRSP0. This allows the SDHC to
avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.
When the SDHC modifies part of the command response registers, as shown in the table
above, it preserves the unmodified bits.
Address: SDHC_CMDRSP3 is 400B_1000h base + 1Ch offset = 400B_101Ch
1256
Bit
W
R1b (Auto CMD12 response)
R
R1,R1b (normal response)
R2 (CID, CSD register)
31
0
R3 (OCR register)
R4 (OCR register)
R6 (Publish RCA)
Response type
30
0
R5, R5b
29
0
28
0
27
Table 45-13. Response bit definition for each response type
0
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Card status for auto CMD12
New published RCA[31:16]
OCR register for memory
CID/CSD register [127:8]
OCR register for I/O etc.
23
0
Meaning of response
and card status[15:0]
22
0
SDIO response
Card status
21
0
20
0
19
0
18
0
17
0
CMDRSP3
16
0
15
0
14
0
Response field
13
0
R[127:8]
R[39:8]
R[39:8]
R[39:8]
R[39:8]
R[39:8]
R[39:9]
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
CMDRSP2, CMDRSP1,
0
Response register
6
{CMDRSP3[23:0],
CMDRSP0}
0
5
CMDRSP0
CMDRSP3
CMDRSP0
CMDRSP0
CMDRSP0
CMDRSP0
4
0
0
3
0
2
0
1
0
0