MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 507

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
• The time-out value of the watchdog should be set to a minimum of four watchdog
• You must take care not only to refresh the watchdog within the watchdog timer's
• Updates cannot be made in the bus clock cycle immediately following the write of
• It should be ensured that the time-out value for the watchdog is always greater than
• An attempted refresh operation, in between the two writes of the unlock sequence
• Trying to unlock the watchdog within the WCT time after an initial unlock has no
• The refresh and unlock operations and interrupt are not automatically disabled in the
• After emerging from a reset due to a watchdog functional test, you are still expected
• After emerging from a reset due to a watchdog functional test, you still need to go
• You must ensure that both the clock inputs to the glitchless clock multiplexers are
• There is a gap of two to three watchdog clock cycles from the point that stop mode is
• Consider the case when the first refresh value is written, following which the system
clock cycles. This is to take into account the delay in new settings taking effect in the
watchdog clock domain.
actual time-out period, but also provide enough allowance for the time it takes for the
refresh sequence to be detected by the watchdog timer, on the watchdog clock.
the unlock sequence, but one bus clock cycle later.
2xWCT time + 20 bus clock cycles.
and in the WCT time following a successful unlock, will go undetected.
effect.
watchdog functional test mode.
to go through the mandatory steps of unlocking and configuring the watchdog. The
watchdog continues to be in its functional test mode and therefore you should pull
the watchdog out of the functional test mode within WCT time of reset.
through the mandatory steps of unlocking and configuring the watchdog.
alive during the switching of clocks. Failure to do so results in a loss of clock at their
outputs.
entered to the watchdog timer actually pausing, due to synchronization. The same
holds true for an exit from the stop mode, this time resulting in a two to three
watchdog clock cycle delay in the timer restarting. In case the duration of the stop
mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to
pause.
enters stop mode (with system bus clk still on). Now, if the second refresh value is
not written within 20 bus cycles of the first value, the system is reset (or interrupt-
then-reset if enabled).
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 23 Watchdog Timer (WDOG)
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