MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 877

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 36 FlexTimer (FTM)
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
OUTMASK register is updated and
TRIG0 bit is cleared
Figure 36-217. OUTMASK Synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(SYNCHOM = 1), (PWMSYNC = 1), and (a Hardware Trigger Was Used)
36.4.11.8 INVCTRL Register Synchronization
The INVCTRL register synchronization updates the INVCTRL register with its buffer
value.
The INVCTRL register can be updated at each rising edge of system clock (INVC = 0) or
by the enhanced PWM synchronization (INVC = 1 and SYNCMODE = 1) according to
the following flowchart.
In the case of enhanced PWM synchronization, the INVCTRL register synchronization
depends on SWINVC and HWINVC bits.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
877