MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 97

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

For example, for a device containing 64 KB of SRAM the ranges are:
3.5.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode.
In VLLS2 the 4 KB region of SRAM_U from 0x2000_0000 is powered.
In VLLS1 no SRAM is retained. However, the
VLLS1.
3.5.3.4 SRAM accesses
The SRAM is split into two logical arrays that are 32-bits wide.
The backdoor port makes the SRAM accessible to the non-core bus masters (such as
DMA).
The following figure illustrates the SRAM accesses within the device.
The following simultaneous accesses can be made to different logical halves of the
SRAM:
Freescale Semiconductor, Inc.
• SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_7FFF
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the
• Core code and core system
port.
backdoor port.
Cortex-M4 core
System bus
Code bus
Frontdoor
MPU
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 3-25. SRAM access diagram
SRAM controller
SRAM_U
SRAM_L
32-byte register file
Backdoor
MPU
Crossbar switch
Chapter 3 Chip Configuration
is available in
non-core master
non-core master
non-core master
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