MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 201

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Conversely the debug system is capable of generating system reset using the following
mechanism:
9.7 AHB-AP
AHB-AP provides the debugger access to all memory and registers in the system,
including processor registers through the NVIC. System access is independent of the
processor status. AHB-AP does not do back-to-back transactions on the bus, so all
transactions are non-sequential. AHB-AP can perform unaligned and bit-band
transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP
transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported
sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets
the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch
debugging such as read/stop/reset the core. AHB-AP transactions are little endian.
The MPU includes default settings and protections for the Region Descriptor 0 (RGD0)
such that the Debugger always has access to the entire address space and those rights
cannot be changed by the core or any other bus master.
For a short period at the start of a system reset event the system security status is being
determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP
Status register is accessible and can be monitored to determine when this initial period is
completed. After this initial period, if system reset is held via assertion of the RESET pin,
the debugger has access via the bus matrix to the private peripheral bus to configure the
debug IP even while system reset is asserted. While in system reset, access to other
memory and register resources, accessed over the Crossbar Switch, is blocked.
Freescale Semiconductor, Inc.
• Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the
• TRST asserted via the cJTAG escape command.
• System POR reset
• A system reset in the DAP control register which allows the debugger to hold the
• SYSRESETREQ bit in the NVIC application interrupt and reset control register
• A system reset in the DAP control register which allows the debugger to hold the
TCLK domain that allows the debugger to reset the debug logic.
system in reset.
Core in reset.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 9 Debug
201