MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 15

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Section Number
18.3
18.4
18.5
18.6
19.1
19.2
19.3
Freescale Semiconductor, Inc.
Memory Map/Register Definition.................................................................................................................................349
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
18.3.7
18.3.8
Functional Description..................................................................................................................................................363
18.4.1
18.4.2
18.4.3
Initialization Information..............................................................................................................................................365
Application Information................................................................................................................................................365
Introduction...................................................................................................................................................................369
19.1.1
19.1.2
Memory map/register definition...................................................................................................................................370
19.2.1
19.2.2
19.2.3
Functional Description..................................................................................................................................................385
19.3.1
Control/Error Status Register (MPU_CESR)..............................................................................................352
Error Address Register, Slave Port n (MPU_EARn)...................................................................................354
Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................355
Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................356
Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................357
Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................357
Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................360
Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................361
Access Evaluation Macro.............................................................................................................................363
Putting It All Together and Error Terminations...........................................................................................364
Power Management......................................................................................................................................365
Features........................................................................................................................................................369
General operation.........................................................................................................................................369
Master Privilege Register A (AIPSx_MPRA).............................................................................................371
Peripheral Access Control Register (AIPSx_PACRn).................................................................................375
Peripheral Access Control Register (AIPSx_PACRn).................................................................................380
Access support.............................................................................................................................................385
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Peripheral Bridge (AIPS-Lite)
Chapter 19
Title
Page
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