MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 56

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Module Functional Categories
2.3.3 Memories and Memory Interfaces
The following memories and memory interfaces are available on this device.
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Crossbar switch (XBS)
Memory protection unit (MPU)
Peripheral bridges
DMA multiplexer (DMAMUX)
Direct memory access (DMA) controller
External watchdog monitor (EWM)
Software watchdog (WDOG)
Flash memory
Flash memory controller
SRAM
SRAM controller
System register file
VBAT register file
Serial programming interface (EzPort)
Module
Module
Table 2-4. Memories and memory interfaces
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 2-3. System modules (continued)
The XBS connects bus masters and bus slaves, allowing all bus masters to
access different bus slaves simultaneously and providing arbitration among the
bus masters when they access the same slave.
The MPU provides memory protection and task isolation. It concurrently monitors
all bus master transactions for the slave connections.
The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
The DMA multiplexer selects from many DMA requests down to 16 for the DMA
controller.
The DMA controller provides programmable channels with transfer control
descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128-
bit data values.
The EWM is a redundant mechanism to the software watchdog module that
monitors both internal and external system operation for fail conditions.
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 KHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
Manages the interface between the device and the on-chip flash memory.
Internal system RAM. Partial SRAM kept powered in VLLS2 low leakage mode.
Manages simultaneous accesses to system RAM by multiple master peripherals
and core.
32-byte register file that is accessible during all power modes and is powered by
VDD.
32-byte register file that is accessible during all power modes and is powered by
VBAT.
Same serial interface as, and subset of, the command set used by industry-
standard SPI flash memories. Provides the ability to read, erase, and program
flash memory and reset command to boot the system after flash programming.
• Program flash memory — non-volatile flash memory that can execute
• FlexMemory — encompasses the following memory types:
program code
• Programming acceleration RAM — RAM memory that accelerates
flash programming
Description
Description
Freescale Semiconductor, Inc.