MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 192

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Introduction
The following table presents a brief description of each one of the debug components.
192
JTAG
SWJ-DP+ cJTAG
AHB-AP
JTAG-AP
ROM Table
Core Debug
CoreSight Trace Funnel (not shown in figure)
CoreSight Trace Replicator (not shown in figure)
ETM (Embedded Trace Macrocell)
CoreSight ETB (Embedded Trace Buffer)
ITM
SW/
AWIC
SWJ-DP
INTISR[239:0]
SLEEPDEEP
SLEEPING
INTNMI
NVIC
Module
Private Peripheral Bus
MDM-AP
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 9-1. Debug Components Description
AHB-AP
Interrupts
Figure 9-1. Cortex-M4 Debug Topology
(internal)
Debug
Sleep
Table continues on the next page...
Instr.
FPB
Core
Data
Modified Debug Port with support for SWD, JTAG, cJTAG
AHB Master Interface from JTAG to debug module and SOC
system memory maps
Bridge to DFT/BIST resources.
Identifies which debug IP is available.
Singlestep, Register Access, Run, Core Status
The CSTF combines multiple trace streams onto a single
ATB bus.
The ATB replicator enables two trace sinks to be wired
together and operate from the same incoming trace stream.
ETMv3.5 Architecture
Memory mapped buffer used to store trace data.
S/W Instrumentation Messaging + Simple Data Trace
Messaging + Watchpoint Messaging
Matrix
DWT
Bus
Cortex-M4
Trigger
APB
ITM
i/f
System bus
D-code bus
I-code bus
Description
ETB
Freescale Semiconductor, Inc.
TPIU
ETM
Code bus
or multi-pin)
(serial wire
Trace port
ROM
Table
MCM