MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 147

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

AIPS-Lite1 and the general purpose input/output module share the connection to crossbar
switch slave port 3. The AIPS-Lite1 is accessible at locations 0x4008_0000–
0x400F_EFFF. The general purpose input/output module is accessible in a 4-kbyte region
at 0x400F_F000–0x400F_FFFF. Its direct connection to the crossbar switch provides
master access without incurring wait states associated with accesses via the AIPS-Lite
controllers.
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
Freescale Semiconductor, Inc.
System 32-bit base address
0x4000_A000
0x4000_B000
0x4000_C000
0x4000_D000
0x4000_E000
0x4000_0000
0x4000_1000
0x4000_2000
0x4000_3000
0x4000_4000
0x4000_5000
0x4000_6000
0x4000_7000
0x4000_8000
0x4000_9000
0x4000_F000
0x4001_0000
0x4001_1000
0x4001_2000
Table 4-2. Peripheral bridge 0 slot assignments
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
number
Slot
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
Table continues on the next page...
Peripheral bridge 0 (AIPS-Lite 0)
—
—
—
Crossbar switch
—
—
—
DMA controller
DMA controller transfer control descriptors
—
—
—
MPU
—
—
—
—
—
Module
Chapter 4 Memory Map
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