MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 569

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

27.4.1 Flash Access Protection Register (FMC_PFAPR)
Address: FMC_PFAPR is 4001_F000h base + 0h offset = 4001_F000h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
Reserved
R
R
M7PFD
M6PFD
M5PFD
M4PFD
31–24
Field
23
22
21
20
M7AP[1:0]
31
15
0
0
30
14
0
0
This read-only field is reserved and always has the value zero.
Master 7 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0
1
Master 6 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0
1
Master 5 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0
1
Master 4 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
Prefetching for this master is enabled.
Prefetching for this master is disabled.
Prefetching for this master is enabled.
Prefetching for this master is disabled.
Prefetching for this master is enabled.
Prefetching for this master is disabled.
M6AP[1:0]
29
13
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
0
M5AP[1:0]
27
11
0
0
FMC_PFAPR field descriptions
Table continues on the next page...
26
10
0
0
M4AP[1:0]
25
0
0
9
24
0
0
8
Description
M3AP[1:0]
23
1
0
7
22
1
0
6
Chapter 27 Flash Memory Controller (FMC)
M2AP[1:0]
21
1
1
5
20
1
1
4
M1AP[1:0]
19
1
1
3
18
0
1
2
M0AP[1:0]
17
0
1
1
16
0
1
0
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