MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1187

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
Reserved
TXEMPT
RXEMPT
RXUF
TXOF
Field
5–2
7
6
1
0
Transmit Buffer/FIFO Empty
This status bit asserts when there is no data in the Transmit FIFO/buffer. This bit does not take into
account data that is in the transmit shift register.
0
1
Receive Buffer/FIFO Empty
This status bit asserts when there is no data in the receive FIFO/Buffer. This bit does not take into
account data that is in the receive shift register.
0
1
This read-only field is reserved and always has the value zero.
Transmitter Buffer Overflow Flag
This flag indicates that more data has been written to the transmit buffer than it can hold. This bit will
assert regardless of the value of CFIFO[TXOFE]. However, an interrupt will only be issued to the host if
the CFIFO[TXOFE] bit is set. This flag is cleared by writing a "1".
0
1
Receiver Buffer Underflow Flag
This flag indicates that more data has been read from the receive buffer than was present. This bit will
assert regardless of the value of CFIFO[RXUFE]. However, an interrupt will only be issued to the host if
the CFIFO[RXUFE] bit is set. This flag is cleared by writing a "1".
0
1
Transmit buffer is not empty.
Transmit buffer is empty.
Receive buffer is not empty.
Receive buffer is empty.
No transmit buffer overflow has occurred since the last time the flag was cleared.
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
No receive buffer underflow has occurred since the last time the flag was cleared.
At least one receive buffer underflow has occurred since the last time the flag was cleared.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
UARTx_SFIFO field descriptions
Chapter 44 Universal Asynchronous Receiver/Transmitter (UART)
Description
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