MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 737

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

32.8.4 Low Pass Filter
The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted
comparator output COUTA and generates the filtered and synchronized output COUT.
Both COUTA and COUT can be configured as module outputs and are used for different
purposes within the system.
Synchronization and edge detection are always used to determine status register bit
values. They also apply to COUT for all sampling and windowed modes. Filtering can be
performed using an internal timebase defined by FPR[FILT_PER], or using an external
SAMPLE input to determine sample time.
The need for digital filtering and the amount of filtering is dependent on user
requirements. Filtering can become more useful in the absence of an external hysteresis
circuit. Without external hysteresis, high frequency oscillations can be generated at
COUTA when the selected INM and INP input voltages differ by less than the offset
voltage of the differential comparator.
32.8.4.1 Enabling Filter Modes
Filter Modes are enabled by setting CR0[FILTER_CNT] greater than 0x01 and (setting
FPR[FILT_PER] to a non-zero value OR setting CR1[SE]=1). If using the divided bus
clock to drive the filter, it will take samples of COUTA every FPR[FILT_PER] bus clock
cycles.
The filter output will be at logic zero when first initalized, and will subsequently change
when CR0[FILTER_CNT] consecutive samples all agree that the output value has
changed. Said another way, SCR[COUT] will be zero for some initial period, even when
COUTA is at logic one.
Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates
switching current associated with the filtering process.
Freescale Semiconductor, Inc.
Always switch to this setting prior to making any changes in
filter parameters. This resets the filter to a known state.
Switching CR0[FILTER_CNT] on the fly without this
intermediate step can result in unexpected behavior.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Note
Chapter 32 Comparator (CMP)
737