MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 432

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
21.3.11 Clear Error Register (DMA_CERR)
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CERR is 4000_8000h base + 1Eh offset = 4000_801Eh
432
Reserved
CERR
CAEI
NOP
Reset
Field
Read
5–4
3–0
Write
7
6
Bit
NOP
0
1
Clear All Error Indicators
0
1
This field is reserved.
Clear Error Indicator
Clears the corresponding bit in ERR
7
0
0
Normal operation
No operation, ignore the other bits in this register
Clear only the ERR bit specified in the CERR field
Clear all bits in ERR
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CAEI
0
0
6
DMA_CERR field descriptions
0
5
0
0
4
Description
0
3
0
2
CERR
Freescale Semiconductor, Inc.
0
0
1
0
0