MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 514

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
24.3.1 MCG Control 1 Register (MCG_C1)
Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000h
514
IREFSTEN
IRCLKEN
FRDIV
IREFS
CLKS
Reset
Field
Read
7–6
5–3
Write
2
1
0
Bit
Clock Source Select
Selects the clock source for MCGOUTCLK .
00
01
10
11
FLL External Reference Divider
Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must
be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for
MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases
when trying to enter a FLL mode from FBE).
000
001
010
011
100
101
110
111
Internal Reference Select
Selects the reference clock source for the FLL.
0
1
Internal Reference Clock Enable
Enables the internal reference clock for use as MCGIRCLK.
0
1
Internal Reference Stop Enable
Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
7
0
External reference clock is selected.
The slow internal reference clock is selected.
MCGIRCLK inactive.
MCGIRCLK active.
Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit).
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Encoding 3 — Reserved, defaults to 00.
CLKS
If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved .
If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved .
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
MCG_C1 field descriptions
Table continues on the next page...
0
5
FRDIV
0
4
Description
0
3
IREFS
1
2
Freescale Semiconductor, Inc.
IRCLKEN
0
1
IREFSTEN
0
0