MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 426

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

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Part Number:
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Memory map/register definition
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte
registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CEEI is 4000_8000h base + 18h offset = 4000_8018h
426
Reserved
CAEE
CEEI
EEI1
EEI0
NOP
Field
Reset
Field
Read
5–4
3–0
Write
1
0
7
6
Bit
NOP
0
1
Enable Error Interrupt 1
0
1
Enable Error Interrupt 0
0
1
0
1
Clear All Enable Error Interrupts
0
1
This field is reserved.
Clear Enable Error Interrupt
Clears the corresponding bit in EEI
7
0
0
The error signal for corresponding channel does not generate an error interrupt
The assertion of the error signal for corresponding channel generates an error interrupt request
The error signal for corresponding channel does not generate an error interrupt
The assertion of the error signal for corresponding channel generates an error interrupt request
The error signal for corresponding channel does not generate an error interrupt
The assertion of the error signal for corresponding channel generates an error interrupt request
Normal operation
No operation, ignore the other bits in this register
Clear only the EEI bit specified in the CEEI field
Clear all bits in EEI
CAEE
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
0
6
DMA_EEI field descriptions (continued)
DMA_CEEI field descriptions
0
5
0
0
4
Description
Description
0
3
0
2
CEEI
Freescale Semiconductor, Inc.
0
0
1
0
0

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