MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 235

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
Reserved
Reserved
Reserved
14–11
10–8
MUX
ODE
Field
DSE
PFE
LK
15
7
6
5
4
3
1001
1010
1011
1100
Others Reserved.
Lock Register
0
1
This read-only field is reserved and always has the value zero.
Pin Mux Control
The corresponding pin is configured as follows:
000
001
010
011
100
101
110
111
This read-only field is reserved and always has the value zero.
Drive Strength Enable
Drive Strength configuration is valid in all digital pin muxing modes.
0
1
Open Drain Enable
Open Drain configuration is valid in all digital pin muxing modes.
0
1
Passive Filter Enable
Passive Filter configuration is valid in all digital pin muxing modes.
0
1
This read-only field is reserved and always has the value zero.
Pin Control Register bits [15:0] are not locked.
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
Open Drain output is disabled on the corresponding pin.
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
Passive Input Filter is disabled on the corresponding pin.
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input.
A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the
Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
Pin Disabled (Analog).
Alternative 1 (GPIO).
Alternative 2 (chip specific).
Alternative 3 (chip specific).
Alternative 4 (chip specific).
Alternative 5 (chip specific).
Alternative 6 (chip specific).
Alternative 7 (chip specific / JTAG / NMI).
Interrupt on rising edge.
Interrupt on falling edge.
Interrupt on either edge.
Interrupt when logic one.
PORTx_PCRn field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 11 Port control and interrupts (PORT)
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